On nominal delay minimization in LUT-based FPGA technology mapping.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/integration/CongD94
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/integration/CongD94
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Jason_Cong
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Yuzheng_Ding
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1016%2F0167-9260%2894%2990012-4
>
foaf:
homepage
<
https://doi.org/10.1016/0167-9260(94)90012-4
>
dc:
identifier
DBLP journals/integration/CongD94
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1016%2F0167-9260%2894%2990012-4
(xsd:string)
dcterms:
issued
1994
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/integration
>
rdfs:
label
On nominal delay minimization in LUT-based FPGA technology mapping.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Jason_Cong
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Yuzheng_Ding
>
swrc:
number
1
(xsd:string)
swrc:
pages
73-94
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/integration/CongD94/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/integration/CongD94
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/integration/integration18.html#CongD94
>
rdfs:
seeAlso
<
https://doi.org/10.1016/0167-9260(94)90012-4
>
dc:
title
On nominal delay minimization in LUT-based FPGA technology mapping.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
18
(xsd:string)