A read-decoupled gated-ground SRAM architecture for low-power embedded memories.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/integration/HussainJ12
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A read-decoupled gated-ground SRAM architecture for low-power embedded memories.
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A read-decoupled gated-ground SRAM architecture for low-power embedded memories.
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