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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/integration/MakSCL10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/N._Pete_Sedcole>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Peter_Y._K._Cheung>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Terrence_S._T._Mak>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wayne_Luk>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1016%2Fj.vlsi.2010.01.002>
foaf:homepage <https://doi.org/10.1016/j.vlsi.2010.01.002>
dc:identifier DBLP journals/integration/MakSCL10 (xsd:string)
dc:identifier DOI doi.org%2F10.1016%2Fj.vlsi.2010.01.002 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/integration>
rdfs:label Wave-pipelined intra-chip signaling for on-FPGA communications. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/N._Pete_Sedcole>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Peter_Y._K._Cheung>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Terrence_S._T._Mak>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wayne_Luk>
swrc:number 2 (xsd:string)
swrc:pages 188-201 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/integration/MakSCL10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/integration/MakSCL10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/integration/integration43.html#MakSCL10>
rdfs:seeAlso <https://doi.org/10.1016/j.vlsi.2010.01.002>
dc:title Wave-pipelined intra-chip signaling for on-FPGA communications. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 43 (xsd:string)