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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/integration/RoutANN24>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Debasish_Nayak>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Debiprasad_Priyabrata_Acharya>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Prakash_Kumar_Rout>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Umakanta_Nanda>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1016%2Fj.vlsi.2023.102100>
foaf:homepage <https://doi.org/10.1016/j.vlsi.2023.102100>
dc:identifier DBLP journals/integration/RoutANN24 (xsd:string)
dc:identifier DOI doi.org%2F10.1016%2Fj.vlsi.2023.102100 (xsd:string)
dcterms:issued 2024 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/integration>
rdfs:label Design of robust analog integrated circuit based on process corner performance variability minimization. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Debasish_Nayak>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Debiprasad_Priyabrata_Acharya>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Prakash_Kumar_Rout>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Umakanta_Nanda>
swrc:month January (xsd:string)
swrc:pages 102100 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/integration/RoutANN24/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/integration/RoutANN24>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/integration/integration94.html#RoutANN24>
rdfs:seeAlso <https://doi.org/10.1016/j.vlsi.2023.102100>
dc:title Design of robust analog integrated circuit based on process corner performance variability minimization. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 94 (xsd:string)