A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/integration/SerafySS14
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A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs.
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A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs.
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