Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/journals/integration/WangTTLWC16>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Jinn-Shyan_Wang>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Po-Hao_Wang>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Rizal_Tanjung>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Shang-Jen_Tsai>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Tay-Jyi_Lin>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Tien-Fu_Chen>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1016%2Fj.vlsi.2016.01.001>
foaf:homepage	<https://doi.org/10.1016/j.vlsi.2016.01.001>
dc:identifier	DBLP journals/integration/WangTTLWC16 (xsd:string)
dc:identifier	DOI doi.org%2F10.1016%2Fj.vlsi.2016.01.001 (xsd:string)
dcterms:issued	2016 (xsd:gYear)
swrc:journal	<https://dblp.l3s.de/d2r/resource/journals/integration>
rdfs:label	Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Jinn-Shyan_Wang>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Po-Hao_Wang>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Rizal_Tanjung>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Shang-Jen_Tsai>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Tay-Jyi_Lin>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Tien-Fu_Chen>
swrc:pages	24-36 (xsd:string)
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dc:title	Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors. (xsd:string)
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