Self authentication path insertion in FPGA-based design flow for tamper-resistant purpose.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/isecure/Zamanzadeh016
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Self authentication path insertion in FPGA-based design flow for tamper-resistant purpose.
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Self authentication path insertion in FPGA-based design flow for tamper-resistant purpose.
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