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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/jacm/IshiiLP97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alexander_T._Ishii>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Charles_E._Leiserson>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marios_C._Papaefthymiou>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F256292.256301>
foaf:homepage <https://doi.org/10.1145/256292.256301>
dc:identifier DBLP journals/jacm/IshiiLP97 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F256292.256301 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/jacm>
rdfs:label Optimizing two-phase, level-clocked circuitry. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alexander_T._Ishii>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Charles_E._Leiserson>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marios_C._Papaefthymiou>
swrc:number 1 (xsd:string)
swrc:pages 148-199 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/jacm/IshiiLP97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/jacm/IshiiLP97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/jacm/jacm44.html#IshiiLP97>
rdfs:seeAlso <https://doi.org/10.1145/256292.256301>
dc:subject VLSI, clock tuning, level-clocked circuitry, multiphase clocking, retiming, timing analysis and optimization (xsd:string)
dc:title Optimizing two-phase, level-clocked circuitry. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 44 (xsd:string)