Optimizing two-phase, level-clocked circuitry.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/jacm/IshiiLP97
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dcterms:
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https://dblp.l3s.de/d2r/resource/authors/Charles_E._Leiserson
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https://dblp.l3s.de/d2r/resource/authors/Marios_C._Papaefthymiou
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1997
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Optimizing two-phase, level-clocked circuitry.
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1
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148-199
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dc:
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VLSI, clock tuning, level-clocked circuitry, multiphase clocking, retiming, timing analysis and optimization
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title
Optimizing two-phase, level-clocked circuitry.
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44
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