Verification of FPGA Layout Generators in Higher-Order Logic. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Oliver_Pell>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1007%2Fs10817-006-9039-9>
foaf:homepage	<https://doi.org/10.1007/s10817-006-9039-9>
dc:identifier	DBLP journals/jar/Pell06 (xsd:string)
dc:identifier	DOI doi.org%2F10.1007%2Fs10817-006-9039-9 (xsd:string)
dcterms:issued	2006 (xsd:gYear)
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rdfs:label	Verification of FPGA Layout Generators in Higher-Order Logic. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Oliver_Pell>
swrc:number	1-2 (xsd:string)
swrc:pages	117-152 (xsd:string)
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rdfs:seeAlso	<https://doi.org/10.1007/s10817-006-9039-9>
dc:subject	FPGA; layout description; circuit verification; theorem proving (xsd:string)
dc:title	Verification of FPGA Layout Generators in Higher-Order Logic. (xsd:string)
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