A nonlinear optimization methodology for VLSI fixed-outline floorplanning.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/jco/LuoAV08
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2008
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A nonlinear optimization methodology for VLSI fixed-outline floorplanning.
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4
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378-401
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Circuit layout design; VLSI floorplanning; Facility layout; Combinatorial optimization; Global optimization; Convex programming
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A nonlinear optimization methodology for VLSI fixed-outline floorplanning.
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