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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/jcsc/GannaSP22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Govind_Singh_Patel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Raju_Ganna>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shanky_Saxena>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1142%2FS0218126622502929>
foaf:homepage <https://doi.org/10.1142/S0218126622502929>
dc:identifier DBLP journals/jcsc/GannaSP22 (xsd:string)
dc:identifier DOI doi.org%2F10.1142%2FS0218126622502929 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/jcsc>
rdfs:label Design of Power, Area and Delay Optimized Direct Digital Synthesizer Using Modified 32-Bit Square Root Carry Select Adder. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Govind_Singh_Patel>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Raju_Ganna>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shanky_Saxena>
swrc:number 17 (xsd:string)
swrc:pages 2250292:1-2250292:23 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/jcsc/GannaSP22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/jcsc/GannaSP22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/jcsc/jcsc31.html#GannaSP22>
rdfs:seeAlso <https://doi.org/10.1142/S0218126622502929>
dc:title Design of Power, Area and Delay Optimized Direct Digital Synthesizer Using Modified 32-Bit Square Root Carry Select Adder. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 31 (xsd:string)