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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/jcsc/JayashreePA18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/H._V._Jayashree>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sharan_Patil>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vinod_Kumar_Agrawal>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1142%2FS0218126618500482>
foaf:homepage <https://doi.org/10.1142/S0218126618500482>
dc:identifier DBLP journals/jcsc/JayashreePA18 (xsd:string)
dc:identifier DOI doi.org%2F10.1142%2FS0218126618500482 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/jcsc>
rdfs:label Design Approaches for Resource and Performance Optimization of Reversible BCD Addition and Unified BCD Addition/Subtraction Circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/H._V._Jayashree>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sharan_Patil>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vinod_Kumar_Agrawal>
swrc:number 3 (xsd:string)
swrc:pages 1850048:1-1850048:28 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/jcsc/JayashreePA18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/jcsc/JayashreePA18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/jcsc/jcsc27.html#JayashreePA18>
rdfs:seeAlso <https://doi.org/10.1142/S0218126618500482>
dc:title Design Approaches for Resource and Performance Optimization of Reversible BCD Addition and Unified BCD Addition/Subtraction Circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 27 (xsd:string)