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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/jcsc/JiangMSWH16>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jianfei_Jiang_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Qin_Wang_0009>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Weifeng_He>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Weiguang_Sheng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhigang_Mao>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1142%2FS0218126616501218>
foaf:homepage <https://doi.org/10.1142/S0218126616501218>
dc:identifier DBLP journals/jcsc/JiangMSWH16 (xsd:string)
dc:identifier DOI doi.org%2F10.1142%2FS0218126616501218 (xsd:string)
dcterms:issued 2016 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/jcsc>
rdfs:label Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jianfei_Jiang_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Qin_Wang_0009>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Weifeng_He>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Weiguang_Sheng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhigang_Mao>
swrc:number 10 (xsd:string)
swrc:pages 1650121:1-1650121:31 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/jcsc/JiangMSWH16/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/jcsc/JiangMSWH16>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/jcsc/jcsc25.html#JiangMSWH16>
rdfs:seeAlso <https://doi.org/10.1142/S0218126616501218>
dc:title Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 25 (xsd:string)