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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/jcst/SunYZTC08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dong_Tong_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Han-Xin_Sun>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kun-Peng_Yang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xu_Cheng_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yulai_Zhao_0003>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs11390-008-9117-z>
foaf:homepage <https://doi.org/10.1007/s11390-008-9117-z>
dc:identifier DBLP journals/jcst/SunYZTC08 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs11390-008-9117-z (xsd:string)
dcterms:issued 2008 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/jcst>
rdfs:label CASA: A New IFU Architecture for Power-Efficient Instruction Cache and TLB Designs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dong_Tong_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Han-Xin_Sun>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kun-Peng_Yang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xu_Cheng_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yulai_Zhao_0003>
swrc:number 1 (xsd:string)
swrc:pages 141-153 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/jcst/SunYZTC08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/jcst/SunYZTC08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/jcst/jcst23.html#SunYZTC08>
rdfs:seeAlso <https://doi.org/10.1007/s11390-008-9117-z>
dc:subject computer architecture; instruction cache; instruction TLB; instruction fetch unit; power-efficient design; dynamic voltage scaling (xsd:string)
dc:title CASA: A New IFU Architecture for Power-Efficient Instruction Cache and TLB Designs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 23 (xsd:string)