A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/jcst/XiaWA05
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2005
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A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock.
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CMOS; flip-flops; multiple-valued clock; multiple-valued logic
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A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock.
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