A 485ps 64-Bit Parallel Adder in 0.18mum CMOS.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/jcst/ZhengSLF07
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2007
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A 485ps 64-Bit Parallel Adder in 0.18mum CMOS.
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parallel prefix adder; semi-dynamic; sparse-tree
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A 485ps 64-Bit Parallel Adder in 0.18mum CMOS.
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