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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/jcst/ZhouL05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dian_Zhou>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ruiming_Li>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs11390-005-0147-5>
foaf:homepage <https://doi.org/10.1007/s11390-005-0147-5>
dc:identifier DBLP journals/jcst/ZhouL05 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs11390-005-0147-5 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/jcst>
rdfs:label Design and Verification of High-Speed VLSI Physical Design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dian_Zhou>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ruiming_Li>
swrc:number 2 (xsd:string)
swrc:pages 147-165 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/jcst/ZhouL05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/jcst/ZhouL05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/jcst/jcst20.html#ZhouL05>
rdfs:seeAlso <https://doi.org/10.1007/s11390-005-0147-5>
dc:subject VLSI; physical design; floorplanning and placement; interconnect; delay; wire sizing; buffer insertion; power; order reduction; power grid; parameter extraction; clock distribution (xsd:string)
dc:title Design and Verification of High-Speed VLSI Physical Design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 20 (xsd:string)