Timing-Optimized Hardware Implementation to Accelerate Polynomial Multiplication in the NTRU Algorithm.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/jetc/Camacho-RuizSBM21
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Timing-Optimized Hardware Implementation to Accelerate Polynomial Multiplication in the NTRU Algorithm.
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Timing-Optimized Hardware Implementation to Accelerate Polynomial Multiplication in the NTRU Algorithm.
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