Multilayer stacking technology using wafer-to-wafer stacked method.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/jetc/MiyakawaHMNSNT08
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dcterms:
bibliographicCitation
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http://dblp.uni-trier.de/rec/bibtex/journals/jetc/MiyakawaHMNSNT08
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https://dblp.l3s.de/d2r/resource/authors/Eiri_Hashimoto
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https://dblp.l3s.de/d2r/resource/authors/Natsuo_Nakamura
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https://dblp.l3s.de/d2r/resource/authors/Nobuaki_Miyakawa
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https://dblp.l3s.de/d2r/resource/authors/Shigeto_Nakayama
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https://dblp.l3s.de/d2r/resource/authors/Shinjiro_Toyoda
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https://dblp.l3s.de/d2r/resource/authors/Takanori_Maebashi
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http://dx.doi.org/doi.org%2F10.1145%2F1412587.1412593
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issued
2008
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https://dblp.l3s.de/d2r/resource/journals/jetc
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rdfs:
label
Multilayer stacking technology using wafer-to-wafer stacked method.
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4
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dc:
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3D integration, design, hardware, stacking process
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title
Multilayer stacking technology using wafer-to-wafer stacked method.
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