Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/jetc/WangXWLWYDMW16
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/jetc/WangXWLWYDMW16
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Haoran_Li_0002
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Jiang_Xu_0001
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Luan_H._K._Duong
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Peng_Yang_0003
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Rafael_K._V._Maeda
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Xuan_Wang_0001
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Zhe_Wang_0003
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Zhifei_Wang
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1145%2F2914791
>
foaf:
homepage
<
https://doi.org/10.1145/2914791
>
dc:
identifier
DBLP journals/jetc/WangXWLWYDMW16
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1145%2F2914791
(xsd:string)
dcterms:
issued
2016
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/jetc
>
rdfs:
label
Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Haoran_Li_0002
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Jiang_Xu_0001
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Luan_H._K._Duong
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Peng_Yang_0003
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Rafael_K._V._Maeda
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Xuan_Wang_0001
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Zhe_Wang_0003
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Zhifei_Wang
>
swrc:
number
2
(xsd:string)
swrc:
pages
19:1-19:24
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/jetc/WangXWLWYDMW16/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/jetc/WangXWLWYDMW16
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/jetc/jetc13.html#WangXWLWYDMW16
>
rdfs:
seeAlso
<
https://doi.org/10.1145/2914791
>
dc:
title
Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
13
(xsd:string)