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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/jip/YoshikawaSISN23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Akira_Sato>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hiroaki_Nishikawa>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Makoto_Iwata>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Senri_Yoshikawa>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shuji_Sannomiya>
foaf:homepage <http://dx.doi.org/doi.org%2F10.2197%2Fipsjjip.31.495>
foaf:homepage <https://doi.org/10.2197/ipsjjip.31.495>
dc:identifier DBLP journals/jip/YoshikawaSISN23 (xsd:string)
dc:identifier DOI doi.org%2F10.2197%2Fipsjjip.31.495 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/jip>
rdfs:label EDA-oriented FPGA Circuit Design Method for Four-phase Bundled-data Circular Self-timed Pipeline. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Akira_Sato>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hiroaki_Nishikawa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Makoto_Iwata>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Senri_Yoshikawa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shuji_Sannomiya>
swrc:pages 495-508 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/jip/YoshikawaSISN23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/jip/YoshikawaSISN23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/jip/jip31.html#YoshikawaSISN23>
rdfs:seeAlso <https://doi.org/10.2197/ipsjjip.31.495>
dc:title EDA-oriented FPGA Circuit Design Method for Four-phase Bundled-data Circular Self-timed Pipeline. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 31 (xsd:string)