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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/jolpe/BanerjeeMMPC11>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dhiraj_K._Pradhan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jimson_Mathew>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Maciej_J._Ciesielski>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Saraju_P._Mohanty>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shibaji_Banerjee>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1166%2Fjolpe.2011.1160>
foaf:homepage <https://doi.org/10.1166/jolpe.2011.1160>
dc:identifier DBLP journals/jolpe/BanerjeeMMPC11 (xsd:string)
dc:identifier DOI doi.org%2F10.1166%2Fjolpe.2011.1160 (xsd:string)
dcterms:issued 2011 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/jolpe>
rdfs:label A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dhiraj_K._Pradhan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jimson_Mathew>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Maciej_J._Ciesielski>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Saraju_P._Mohanty>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shibaji_Banerjee>
swrc:number 4 (xsd:string)
swrc:pages 471-481 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/jolpe/BanerjeeMMPC11/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/jolpe/BanerjeeMMPC11>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/jolpe/jolpe7.html#BanerjeeMMPC11>
rdfs:seeAlso <https://doi.org/10.1166/jolpe.2011.1160>
dc:title A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 7 (xsd:string)