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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/jpdc/PalchaudhuriAD22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anindya_Sundar_Dhar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ayan_Palchaudhuri>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Digvijay_Anand>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1016%2Fj.jpdc.2022.04.020>
foaf:homepage <https://doi.org/10.1016/j.jpdc.2022.04.020>
dc:identifier DBLP journals/jpdc/PalchaudhuriAD22 (xsd:string)
dc:identifier DOI doi.org%2F10.1016%2Fj.jpdc.2022.04.020 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/jpdc>
rdfs:label FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anindya_Sundar_Dhar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ayan_Palchaudhuri>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Digvijay_Anand>
swrc:pages 50-63 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/jpdc/PalchaudhuriAD22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/jpdc/PalchaudhuriAD22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/jpdc/jpdc167.html#PalchaudhuriAD22>
rdfs:seeAlso <https://doi.org/10.1016/j.jpdc.2022.04.020>
dc:title FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 167 (xsd:string)