Implications of VHDL timing models on simulation and software synthesis.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/jsa/KrishnaswamyGB97
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/jsa/KrishnaswamyGB97
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Prithviraj_Banerjee
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Rajesh_Gupta_0001
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Venkatram_Krishnaswamy
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1016%2F1383-7621%2897%2980001-X
>
foaf:
homepage
<
https://doi.org/10.1016/1383-7621(97)80001-X
>
dc:
identifier
DBLP journals/jsa/KrishnaswamyGB97
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1016%2F1383-7621%2897%2980001-X
(xsd:string)
dcterms:
issued
1997
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/jsa
>
rdfs:
label
Implications of VHDL timing models on simulation and software synthesis.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Prithviraj_Banerjee
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Rajesh_Gupta_0001
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Venkatram_Krishnaswamy
>
swrc:
number
1
(xsd:string)
swrc:
pages
23-36
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/jsa/KrishnaswamyGB97/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/jsa/KrishnaswamyGB97
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/jsa/jsa44.html#KrishnaswamyGB97
>
rdfs:
seeAlso
<
https://doi.org/10.1016/1383-7621(97)80001-X
>
dc:
title
Implications of VHDL timing models on simulation and software synthesis.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
44
(xsd:string)