A 0.5-9.5-GHz, 1.2-¬Ķs Lock-Time Fractional-N DPLL With ¬Ī1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling.
(xsd:string)
A 0.5-9.5-GHz, 1.2-¬Ķs Lock-Time Fractional-N DPLL With ¬Ī1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling.
(xsd:string)