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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/jssc/BaileySNMKLCT22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_Cassan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Davide_Tonietto>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ehud_Nir>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Grigory_Marderfeld>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hossein_Shakiba>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/James_Bailey_0002>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marc-Andre_LaCroix>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Peter_Krotnev>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FJSSC.2021.3109167>
foaf:homepage <https://doi.org/10.1109/JSSC.2021.3109167>
dc:identifier DBLP journals/jssc/BaileySNMKLCT22 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FJSSC.2021.3109167 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/jssc>
rdfs:label A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_Cassan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Davide_Tonietto>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ehud_Nir>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Grigory_Marderfeld>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hossein_Shakiba>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/James_Bailey_0002>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marc-Andre_LaCroix>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Peter_Krotnev>
swrc:number 1 (xsd:string)
swrc:pages 32-43 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/jssc/BaileySNMKLCT22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/jssc/BaileySNMKLCT22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/jssc/jssc57.html#BaileySNMKLCT22>
rdfs:seeAlso <https://doi.org/10.1109/JSSC.2021.3109167>
dc:title A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 57 (xsd:string)