A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Ganesh_S._Dasika>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Karthik_Shivashankar>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Kriszti%E2%88%9A%C2%B0n_Flautner>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Shidhartha_Das>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FJSSC.2010.2079410>
foaf:homepage	<https://doi.org/10.1109/JSSC.2010.2079410>
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rdfs:label	A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation. (xsd:string)
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dc:title	A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation. (xsd:string)
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