Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/jssc/CaiSPMWK19
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/jssc/CaiSPMWK19
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Alex_S._Weddell
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Anand_Savanth
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/James_Myers
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Pranay_Prabhat
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Tom_J._Kazmierski
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Yunpeng_Cai
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FJSSC.2018.2875089
>
foaf:
homepage
<
https://doi.org/10.1109/JSSC.2018.2875089
>
dc:
identifier
DBLP journals/jssc/CaiSPMWK19
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FJSSC.2018.2875089
(xsd:string)
dcterms:
issued
2019
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/jssc
>
rdfs:
label
Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Alex_S._Weddell
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Anand_Savanth
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/James_Myers
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Pranay_Prabhat
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Tom_J._Kazmierski
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Yunpeng_Cai
>
swrc:
number
2
(xsd:string)
swrc:
pages
550-559
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/jssc/CaiSPMWK19/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/jssc/CaiSPMWK19
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/jssc/jssc54.html#CaiSPMWK19
>
rdfs:
seeAlso
<
https://doi.org/10.1109/JSSC.2018.2875089
>
dc:
title
Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
54
(xsd:string)