A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/jssc/ChenKE21
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/jssc/ChenKE21
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Azita_Emami
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Kuan-Chang_Xavier_Chen
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/William_Wei-Ting_Kuo
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FJSSC.2020.3025285
>
foaf:
homepage
<
https://doi.org/10.1109/JSSC.2020.3025285
>
dc:
identifier
DBLP journals/jssc/ChenKE21
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FJSSC.2020.3025285
(xsd:string)
dcterms:
issued
2021
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/jssc
>
rdfs:
label
A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Azita_Emami
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Kuan-Chang_Xavier_Chen
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/William_Wei-Ting_Kuo
>
swrc:
number
3
(xsd:string)
swrc:
pages
750-762
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/jssc/ChenKE21/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/jssc/ChenKE21
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/jssc/jssc56.html#ChenKE21
>
rdfs:
seeAlso
<
https://doi.org/10.1109/JSSC.2020.3025285
>
dc:
title
A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
56
(xsd:string)