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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/jssc/HashimotoKHKTSN18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hideo_Yamashita>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hiroshi_Okano>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hitoshi_Sakurai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kunihiko_Tajiri>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michiharu_Hara>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ryuichi_Nishiyama>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shinichiro_Shirota>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sugio_Satoh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tetsutaro_Hashimoto>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yasumoto_Tomita>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yasushi_Kakimura>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yukihito_Kawabe>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FJSSC.2017.2777101>
foaf:homepage <https://doi.org/10.1109/JSSC.2017.2777101>
dc:identifier DBLP journals/jssc/HashimotoKHKTSN18 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FJSSC.2017.2777101 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/jssc>
rdfs:label An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC Processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hideo_Yamashita>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hiroshi_Okano>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hitoshi_Sakurai>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kunihiko_Tajiri>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michiharu_Hara>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ryuichi_Nishiyama>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shinichiro_Shirota>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sugio_Satoh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tetsutaro_Hashimoto>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yasumoto_Tomita>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yasushi_Kakimura>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yukihito_Kawabe>
swrc:number 4 (xsd:string)
swrc:pages 1028-1037 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/jssc/HashimotoKHKTSN18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/jssc/HashimotoKHKTSN18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/jssc/jssc53.html#HashimotoKHKTSN18>
rdfs:seeAlso <https://doi.org/10.1109/JSSC.2017.2777101>
dc:title An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC Processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 53 (xsd:string)