A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/journals/jssc/HigetaUOFNIYINO96>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Hiroaki_Nambu>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Keiichi_Higeta>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Kenichi_Ohhata>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Kunihiko_Yamaguchi>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Masahiko_Nishiyama>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Masami_Usami>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Masayuki_Ohayashi>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Nadateru_Hanta>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Satoru_Isomura>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Yasuhiro_Fujimura>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Youji_Idei>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2F4.540054>
foaf:homepage	<https://doi.org/10.1109/4.540054>
dc:identifier	DBLP journals/jssc/HigetaUOFNIYINO96 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2F4.540054 (xsd:string)
dcterms:issued	1996 (xsd:gYear)
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rdfs:label	A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Hiroaki_Nambu>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Keiichi_Higeta>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Kenichi_Ohhata>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Kunihiko_Yamaguchi>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Masahiko_Nishiyama>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Masami_Usami>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Masayuki_Ohayashi>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Nadateru_Hanta>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Satoru_Isomura>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Yasuhiro_Fujimura>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Youji_Idei>
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swrc:pages	1443-1450 (xsd:string)
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rdfs:seeAlso	<https://doi.org/10.1109/4.540054>
dc:title	A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry. (xsd:string)
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swrc:volume	31 (xsd:string)