A 0.5-1 V, -68 dB Power Supply Rejection Capacitorless Analog LDO Using Voltage-to-Time Conversion in 28-nm CMOS.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/jssc/JangGKYC22
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A 0.5-1 V, -68 dB Power Supply Rejection Capacitorless Analog LDO Using Voltage-to-Time Conversion in 28-nm CMOS.
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A 0.5-1 V, -68 dB Power Supply Rejection Capacitorless Analog LDO Using Voltage-to-Time Conversion in 28-nm CMOS.
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