A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/jssc/KimLMJCL97
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A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL.
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A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL.
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