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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/jssc/LeeCJLS23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dongsuk_Shin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hoyeon_Jeon>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jae-Gon_Lee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jong-Jin_Lee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Younsik_Choi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FJSSC.2022.3219410>
foaf:homepage <https://doi.org/10.1109/JSSC.2022.3219410>
dc:identifier DBLP journals/jssc/LeeCJLS23 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FJSSC.2022.3219410 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/jssc>
rdfs:label Fully Automated Hardware-Driven Clock-Gating Architecture With Complete Clock Coverage for 4 nm Exynos Mobile SOC. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dongsuk_Shin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hoyeon_Jeon>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jae-Gon_Lee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jong-Jin_Lee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Younsik_Choi>
swrc:number 1 (xsd:string)
swrc:pages 90-101 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/jssc/LeeCJLS23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/jssc/LeeCJLS23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/jssc/jssc58.html#LeeCJLS23>
rdfs:seeAlso <https://doi.org/10.1109/JSSC.2022.3219410>
dc:title Fully Automated Hardware-Driven Clock-Gating Architecture With Complete Clock Coverage for 4 nm Exynos Mobile SOC. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 58 (xsd:string)