Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/jssc/NonisDPS05
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Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture.
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Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture.
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