A 0.5-őľm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/jssc/OgiwaraTIMTDTKS00
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A 0.5-őľm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor.
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A 0.5-őľm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor.
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