A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/jssc/SaekiNFTNSMHMIN96
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dc:
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A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay.
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