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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/jssc/ShigematsuMMTY97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Junzo_Yamada>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Satoshi_Shigematsu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shin%27ichiro_Mutoh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yasuyuki_Matsuya>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yasuyuki_Tanabe>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F4.585288>
foaf:homepage <https://doi.org/10.1109/4.585288>
dc:identifier DBLP journals/jssc/ShigematsuMMTY97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F4.585288 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/jssc>
rdfs:label A 1-V high-speed MTCMOS circuit scheme for power-down application circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Junzo_Yamada>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Satoshi_Shigematsu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shin%27ichiro_Mutoh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yasuyuki_Matsuya>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yasuyuki_Tanabe>
swrc:number 6 (xsd:string)
swrc:pages 861-869 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/jssc/ShigematsuMMTY97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/jssc/ShigematsuMMTY97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/jssc/jssc32.html#ShigematsuMMTY97>
rdfs:seeAlso <https://doi.org/10.1109/4.585288>
dc:title A 1-V high-speed MTCMOS circuit scheme for power-down application circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 32 (xsd:string)