A 2000-MOPS embedded RISC processor with a Rambus DRAM controller.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/jssc/SuzukiDINNMISFA99
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1999
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A 2000-MOPS embedded RISC processor with a Rambus DRAM controller.
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A 2000-MOPS embedded RISC processor with a Rambus DRAM controller.
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