A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/jssc/TakashimaSKTOT99
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1999
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A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive.
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1557-1563
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A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive.
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