A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/journals/jssc/TyhachWSHNWCPKR05>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Bonnie_Wang>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Chiakang_Sung>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Gopinath_Rangan>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Henry_Kim>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Jeffrey_Tyhach>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Johnson_Tan>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Joseph_Huang>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Khai_Nguyen>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Philip_Pan>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Tzung-Chin_Chang>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Xiaobao_Wang>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Yan_Chong>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FJSSC.2005.852156>
foaf:homepage	<https://doi.org/10.1109/JSSC.2005.852156>
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dcterms:issued	2005 (xsd:gYear)
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rdfs:label	A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface. (xsd:string)
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foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Chiakang_Sung>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Gopinath_Rangan>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Henry_Kim>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Jeffrey_Tyhach>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Johnson_Tan>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Joseph_Huang>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Khai_Nguyen>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Philip_Pan>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Tzung-Chin_Chang>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Xiaobao_Wang>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Yan_Chong>
swrc:number	9 (xsd:string)
swrc:pages	1829-1838 (xsd:string)
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rdfs:seeAlso	<https://doi.org/10.1109/JSSC.2005.852156>
dc:title	A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface. (xsd:string)
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