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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/jssc/WangBHKNWZZB10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fatih_Hamzaoglu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kevin_Zhang_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Liqiong_Wei>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mark_Bohr>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pramod_Kolar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Uddalak_Bhattacharya>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yih_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ying_Zhang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yong-Gee_Ng>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FJSSC.2009.2034082>
foaf:homepage <https://doi.org/10.1109/JSSC.2009.2034082>
dc:identifier DBLP journals/jssc/WangBHKNWZZB10 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FJSSC.2009.2034082 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/jssc>
rdfs:label A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fatih_Hamzaoglu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kevin_Zhang_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Liqiong_Wei>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mark_Bohr>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pramod_Kolar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Uddalak_Bhattacharya>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yih_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ying_Zhang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yong-Gee_Ng>
swrc:number 1 (xsd:string)
swrc:pages 103-110 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/jssc/WangBHKNWZZB10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/jssc/WangBHKNWZZB10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/jssc/jssc45.html#WangBHKNWZZB10>
rdfs:seeAlso <https://doi.org/10.1109/JSSC.2009.2034082>
dc:title A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 45 (xsd:string)