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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/jssc/WangCCY15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chun-Yuan_Cheng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jinn-Shyan_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pei-Yuan_Chou>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tzu-Yi_Yang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FJSSC.2015.2466443>
foaf:homepage <https://doi.org/10.1109/JSSC.2015.2466443>
dc:identifier DBLP journals/jssc/WangCCY15 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FJSSC.2015.2466443 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/jssc>
rdfs:label A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chun-Yuan_Cheng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jinn-Shyan_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pei-Yuan_Chou>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tzu-Yi_Yang>
swrc:number 11 (xsd:string)
swrc:pages 2635-2644 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/jssc/WangCCY15/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/jssc/WangCCY15>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/jssc/jssc50.html#WangCCY15>
rdfs:seeAlso <https://doi.org/10.1109/JSSC.2015.2466443>
dc:title A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 50 (xsd:string)