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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/jssc/WangYS00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Duo_Sheng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jinn-Shyan_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Po-Hui_Yang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F4.839918>
foaf:homepage <https://doi.org/10.1109/4.839918>
dc:identifier DBLP journals/jssc/WangYS00 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F4.839918 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/jssc>
rdfs:label Design of a 3-V 300-MHz low-power 8-b√ó8-b pipelined multiplier using pulse-triggered TSPC flip-flops. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Duo_Sheng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jinn-Shyan_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Po-Hui_Yang>
swrc:number 4 (xsd:string)
swrc:pages 583-592 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/jssc/WangYS00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/jssc/WangYS00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/jssc/jssc35.html#WangYS00>
rdfs:seeAlso <https://doi.org/10.1109/4.839918>
dc:title Design of a 3-V 300-MHz low-power 8-b√ó8-b pipelined multiplier using pulse-triggered TSPC flip-flops. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 35 (xsd:string)