Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/jssc/WangZLLWHCLYH24
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/jssc/WangZLLWHCLYH24
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Junjie_Wang_0008
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ru_Huang
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Shaogang_Hu
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Shuang_Liu
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Teng_Zhang
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Tupei_Chen
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Yang_Liu_0062
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Yihe_Liu
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Yuancong_Wu
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Yuchao_Yang
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FJSSC.2023.3304174
>
foaf:
homepage
<
https://doi.org/10.1109/JSSC.2023.3304174
>
dc:
identifier
DBLP journals/jssc/WangZLLWHCLYH24
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FJSSC.2023.3304174
(xsd:string)
dcterms:
issued
2024
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/jssc
>
rdfs:
label
Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Junjie_Wang_0008
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ru_Huang
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Shaogang_Hu
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Shuang_Liu
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Teng_Zhang
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Tupei_Chen
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Yang_Liu_0062
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Yihe_Liu
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Yuancong_Wu
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Yuchao_Yang
>
swrc:
month
February
(xsd:string)
swrc:
number
2
(xsd:string)
swrc:
pages
595-604
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/jssc/WangZLLWHCLYH24/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/jssc/WangZLLWHCLYH24
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/jssc/jssc59.html#WangZLLWHCLYH24
>
rdfs:
seeAlso
<
https://doi.org/10.1109/JSSC.2023.3304174
>
dc:
title
Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
59
(xsd:string)