A Dynamically and Partially Reconfigurable Implementation of the IDEA Algorithm Using FPGAs and Handel-C.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/jucs/CriadoRSG07
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/jucs/CriadoRSG07
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_M._Granado_Criado
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Juan_Antonio_G%E2%88%9A%E2%89%A5mez_Pulido
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Juan_Manuel_S%E2%88%9A%C2%B0nchez-P%E2%88%9A%C2%A9rez
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Miguel_A._Vega-Rodr%E2%88%9A%E2%89%A0guez
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.3217%2Fjucs-013-03-0407
>
foaf:
homepage
<
https://doi.org/10.3217/jucs-013-03-0407
>
dc:
identifier
DBLP journals/jucs/CriadoRSG07
(xsd:string)
dc:
identifier
DOI doi.org%2F10.3217%2Fjucs-013-03-0407
(xsd:string)
dcterms:
issued
2007
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/jucs
>
rdfs:
label
A Dynamically and Partially Reconfigurable Implementation of the IDEA Algorithm Using FPGAs and Handel-C.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_M._Granado_Criado
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Juan_Antonio_G%E2%88%9A%E2%89%A5mez_Pulido
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Juan_Manuel_S%E2%88%9A%C2%B0nchez-P%E2%88%9A%C2%A9rez
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Miguel_A._Vega-Rodr%E2%88%9A%E2%89%A0guez
>
swrc:
number
3
(xsd:string)
swrc:
pages
407-418
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/jucs/CriadoRSG07/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/jucs/CriadoRSG07
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/jucs/jucs13.html#CriadoRSG07
>
rdfs:
seeAlso
<
https://doi.org/10.3217/jucs-013-03-0407
>
dc:
title
A Dynamically and Partially Reconfigurable Implementation of the IDEA Algorithm Using FPGAs and Handel-C.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
13
(xsd:string)