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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/mam/Jay93a>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chris_Jay>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1016%2F0141-9331%2893%2990061-B>
foaf:homepage <https://doi.org/10.1016/0141-9331(93)90061-B>
dc:identifier DBLP journals/mam/Jay93a (xsd:string)
dc:identifier DOI doi.org%2F10.1016%2F0141-9331%2893%2990061-B (xsd:string)
dcterms:issued 1993 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/mam>
rdfs:label VHDL and synthesis tools provide a generic design entry platform into FPGAs, PLDs and ASICs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chris_Jay>
swrc:number 7 (xsd:string)
swrc:pages 391-398 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/mam/Jay93a/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/mam/Jay93a>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/mam/mam17.html#Jay93a>
rdfs:seeAlso <https://doi.org/10.1016/0141-9331(93)90061-B>
dc:title VHDL and synthesis tools provide a generic design entry platform into FPGAs, PLDs and ASICs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 17 (xsd:string)