A Task-Centric Memory Model for Scalable Accelerator Architectures.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/micro/KelmJLPF10
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2010
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A Task-Centric Memory Model for Scalable Accelerator Architectures.
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accelerator, memory model, parallel architecture, software coherence
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A Task-Centric Memory Model for Scalable Accelerator Architectures.
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