Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/micro/LiangCWB08
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bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/micro/LiangCWB08
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/David_M._Brooks
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Gu-Yeon_Wei
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ramon_Canal
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Xiaoyao_Liang
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FMM.2008.12
>
foaf:
homepage
<
https://doi.org/10.1109/MM.2008.12
>
dc:
identifier
DBLP journals/micro/LiangCWB08
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FMM.2008.12
(xsd:string)
dcterms:
issued
2008
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/micro
>
rdfs:
label
Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/David_M._Brooks
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Gu-Yeon_Wei
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ramon_Canal
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Xiaoyao_Liang
>
swrc:
number
1
(xsd:string)
swrc:
pages
60-68
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/micro/LiangCWB08/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/micro/LiangCWB08
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/micro/micro28.html#LiangCWB08
>
rdfs:
seeAlso
<
https://doi.org/10.1109/MM.2008.12
>
dc:
subject
variability, process variation, caches, dynamic memory
(xsd:string)
dc:
title
Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
28
(xsd:string)