Bringing NoCs to 65 nm.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/micro/PulliniAMAMB07
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dcterms:
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http://dblp.uni-trier.de/rec/bibtex/journals/micro/PulliniAMAMB07
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https://dblp.l3s.de/d2r/resource/authors/Antonio_Pullini
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https://dblp.l3s.de/d2r/resource/authors/David_Atienza
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DOI 10.1109%2FMM.2007.79
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2007
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Bringing NoCs to 65 nm.
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foaf:
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https://dblp.l3s.de/d2r/resource/authors/Antonio_Pullini
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75-85
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dc:
subject
network on chip, deep submicron design, on-chip interconnection networks, design aids, low-power design, power management, multicore architectures
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Bringing NoCs to 65 nm.
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27
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